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Micron says it is abandoning plans to bring 4F² DRAM to market after more than two decades of research, arguing that the design offers limited density gains while adding cost and complexity. The company plans to keep scaling 6F² memory and is developing wafer-bonded and longer-term 3D DRAM approaches; whether rivals can produce 4F² economically at scale remains unknown.
Micron says it will not bring 4F² DRAM to market, ending more than two decades of work on the cell design and choosing instead to extend its established 6F² approach. The decision, presented in a company roadmap webinar on Wednesday, sets Micron apart from Samsung, SK hynix and China’s CXMT, which the source report says are pursuing 4F² designs.
Micron President and Chief Technology Officer Scott DeBoer said the apparent density advantage of moving from 6F² to 4F² does not translate into a comparable practical gain. According to DeBoer, capacitor spacing, rather than the cell’s nominal footprint alone, ultimately limits DRAM density. The 4F² layout would add manufacturing cost and complexity, Micron’s explanation says, without enough density benefit to justify commercial production.
The company’s alternative is to continue scaling 6F² DRAM. Its roadmap says 1δ (1-delta) memory is ramping yields, while 1ε (1-epsilon), which uses advanced wafer bonding, is in development. Micron also listed “ζÅ” and “ηÅ” as future stages for planar DRAM. The source report does not give specific production dates for those later stages.
Micron is also pointing toward 3D DRAM, in which storage-cell layers would be stacked vertically. This is distinct from bonding memory to logic: the proposed 3D approach stacks DRAM cells themselves. The report describes this as a longer-term direction, not a product ready for near-term shipment. Building it would require solving technical problems associated with DRAM’s capacitors, heat and signal integrity.
Micron’s Bet on 6F² Scaling
The choice affects how Micron allocates its engineering effort and manufacturing investment. If 4F² proves costly or delivers little usable density improvement, continuing with 6F² could let the company avoid spending heavily on a difficult redesign while improving its current technology. Micron’s stated rationale is that capacitor requirements constrain gains, even when the cell layout becomes smaller.
But the strategy carries a competitive risk. If Samsung, SK hynix or CXMT can manufacture 4F² memory economically and at scale, Micron could give up a density or cost advantage in products where memory capacity matters. CXMT’s reported aim to put 4F² RAM in server DDR5 registered DIMMs by year-end is a company claim relayed by the source report, not confirmation that those products are shipping or that the process is commercially successful.
The longer-term wager is that further planar scaling will eventually yield to 3D DRAM. That architecture could open a different route to higher density, but the source material does not establish when it will be feasible or which company will reach commercial production first.
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Why DRAM Cells Scale Differently
The “F” in 6F² and 4F² refers to a cell geometry, not a DRAM process-node name or a direct measure of chip dimensions. The geometry describes how a memory cell is arranged; actual size also depends on the manufacturing process. DRAM scaling differs from logic scaling because a DRAM cell combines a transistor with a capacitor, while logic cells are built around switching transistors.
For years, 6F² has been the prevailing cell geometry, and 4F² has been treated as a possible route to greater density. The source report says Micron developed the 4F² concept and had spent more than two decades exploring how to commercialize it before deciding to stop. It also reports that Samsung, SK hynix and CXMT are pursuing their own 4F² designs, but provides no independently verified comparison of their yields, costs or product readiness.
Micron’s roadmap also uses labels such as 1δ and 1ε for successive DRAM generations. These are memory-industry designations, not directly interchangeable with logic foundry node names. The roadmap’s mention of wafer bonding refers to joining wafers or layers in a manufacturing process; it should not be confused with the separate goal of stacking multiple layers of DRAM storage cells in a 3D device.
Costs and Rival Readiness Remain Unknown
The source material does not provide comparative cost, yield or performance data for Micron’s 6F² roadmap and rival 4F² programs. It is not yet clear whether any competitor can make 4F² memory at commercial scale, or whether the design’s added complexity will outweigh its potential density benefits. CXMT’s reported end-of-year target is a stated plan, not evidence that the product has reached customers.
Micron has also not supplied, in the cited account, firm commercialization dates for 1ε, the ζÅ and ηÅ stages, or 3D DRAM. The precise manufacturing challenges, expected capacity gains and costs of a future 3D design remain unspecified. The company’s decision is confirmed as a roadmap direction; its eventual competitive outcome is not.
Roadmap Milestones to Watch
Near-term attention will focus on whether Micron can continue improving 1δ yields and move its 1ε wafer-bonding development toward production. The company’s roadmap identifies these efforts but, in the source material, does not attach detailed launch schedules to every stage.
On the competitive side, readers will be watching for evidence that Samsung, SK hynix or CXMT can move 4F² from development into reliable, cost-effective production. CXMT’s reported target for server DDR5 registered DIMMs by year-end is one milestone to track, though the cited report does not confirm that the target will be met. Longer term, Micron’s progress toward 3D DRAM will depend on whether it can address the architecture’s capacitor, thermal and signal challenges.
Key Questions
What does Micron’s decision mean?
Micron says it will not commercialize 4F² DRAM and will keep developing 6F² memory while pursuing later approaches, including wafer-bonded and 3D DRAM.
Why does Micron say 4F² is not worth pursuing?
Micron CTO Scott DeBoer says capacitor spacing limits density, so shrinking the nominal cell geometry would bring less practical benefit than expected while increasing cost and manufacturing complexity.
Are Micron’s rivals making 4F² DRAM?
The source report says Samsung, SK hynix and CXMT are pursuing 4F² designs. It does not confirm that any has achieved economical, high-volume production. CXMT’s reported server-memory target is a plan, not a verified shipment.
What is 3D DRAM?
It is a proposed design that stacks multiple layers of DRAM storage cells vertically. That differs from simply bonding memory to a logic chip. Micron’s cited roadmap presents 3D DRAM as a longer-term direction, with technical obstacles still to solve.
When will Micron’s next DRAM technologies arrive?
The cited account says 1δ is ramping yields and 1ε is in development, but it does not provide firm commercial dates for those stages or for 3D DRAM.
Source: hothardware.com
